Demystifying the BeiDou B1I Signal: The Engineering Logic Behind the 2.046 Mcps Chip Rate

  1. B1I is not the name of a specific satellite, but rather a “signal designation” within the BeiDou Navigation Satellite System. Its carrier frequency is 1561.098 MHz. All BeiDou-2 (BDS-2) and BeiDou-3 (BDS-3) satellites broadcast the B1I signal on this specific frequency band.

  2. The unit of the Pseudo-Random Noise (PRN) code is Mcps (Mega chips per second), which measures the rate of the “chips” generated purely for spread-spectrum modulation. In contrast, the BeiDou navigation message rate is 50 bps (bits per second), which measures the actual data payload carrying meaningful information (like time and ephemeris).


I. Core Parameters of the BeiDou B1I PRN Code

According to the BeiDou Navigation Satellite System Signal In Space Interface Control Document (ICD), the ranging code of the B1I signal strictly adheres to the following physical parameters:

  • Code Generator Architecture: Generated using dual 11-stage Linear Feedback Shift Registers (LFSR).
  • Polynomials:
  • Code Length: 2046 chips. Theoretically, the maximum sequence period of an 11-stage LFSR is . However, to achieve precise time alignment, BeiDou forces a truncation and resets the registers exactly at the 2046th clock cycle.
  • Chip Rate: 2.046 Mcps.
  • Code Period: 1 millisecond (1 ms). The calculation is straightforward:


II. Why is the Chip Rate Exactly 2.046 Mcps?

This seemingly irregular number is not a random choice. It is backed by profound systems engineering and physical considerations:

1. Alignment with the GNSS Fundamental Atomic Clock Frequency

All Global Navigation Satellite Systems (including GPS, BeiDou, and Galileo) share a unified fundamental frequency, , derived from the onboard atomic clocks. This frequency is strictly defined as 10.23 MHz.

All RF carrier frequencies and PRN chip rates are derived from through simple integer multiplication or division. This elegant design drastically reduces the complexity of receiver hardware (such as ADCs and Phase-Locked Loops) and facilitates multi-constellation interoperability.

  • GPS L1 C/A Code: Mcps
  • BeiDou B1I Code: Mcps

2. Benchmarking and Surpassing GPS: Achieving Higher Ranging Accuracy

During its initial design phase, BeiDou benchmarked itself against GPS, the most mature system at the time. The GPS civilian C/A code operates at 1.023 Mcps.

BeiDou doubled this rate for the B1I signal, raising it to 2.046 Mcps. In the realm of radio physics, what does this actually mean?

  • Halved Chip Width: For the 1.023 Mcps GPS signal, the duration of one chip is approximately 1 microsecond, corresponding to a physical length of about 300 meters (speed of light 1 microsecond). For BeiDou’s 2.046 Mcps, the physical length of a single chip is compressed to roughly 150 meters.
  • Sharper Correlation Peaks: A shorter chip width yields a narrower, sharper correlation peak during the receiver’s correlation integration process. This not only doubles the precision of time-of-arrival measurements (thus improving ranging accuracy) but also significantly mitigates the multipath effect (signal reflections) commonly encountered in urban canyons.

3. Perfectly Engineering the 1-Millisecond “Heartbeat”

In GNSS baseband processing, 1 millisecond (1 ms) is a sacrosanct time epoch.

The BeiDou B1I navigation message operates at 50 bps, meaning a single data bit spans exactly 20 milliseconds. To ensure the most elegant hardware processing, the PRN code period must be perfectly aligned to 1 millisecond. By doing this, exactly 20 complete PRN code periods map seamlessly onto a single data bit. The receiver hardware simply needs to use a 1-millisecond integration rhythm; accumulating 20 such intervals accurately extracts a raw 0 or 1 data bit.

To preserve this 1-millisecond epoch, engineers performed a reverse calculation:
Given a predefined chip rate of 2.046 Mcps, how many chips must exist within 1 millisecond?

This mathematically dictates the ultimate reason why the natural 2047-chip Gold code sequence, generated by the 11-stage LFSR, had to be artificially truncated down to exactly 2046 chips.